A phase locked loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. A typical phase locked loop includes a variable frequency oscillator and a phase detector. The oscillator generates a periodic signal. The phase detector compares the phase of the input signal with the phase of the periodic signal and generates control signals that adjust the oscillator to keep the phases matched.
Keeping the input and output phases locked also implies keeping the input and output frequencies the same. Consequently, in addition to synchronizing phases between signals, a phase locked loop can track an input frequency, or it can generate a frequency that is a multiple of the input frequency.
Such phase locked loops are widely employed in radio, telecommunications, computers and other electronic applications. They can be used to demodulate a signal, recover a signal from a noisy communication channel, generate a stable frequency at multiples of an input frequency (frequency synthesis), or distribute precisely timed clock pulses in digital logic circuits such as microprocessors. Since a single integrated circuit can provide a complete phase locked loop building block, phase locked loops are widely used in modern electronic devices, with output frequencies from a fraction of a hertz up to many gigahertz.
In some cases, it may be desirable for a phase locked loop to be operable over a wide band of frequencies. In order to produce such wide band phase locked loops, a charge pump circuit is typically employed in the loop to generate the control signals sent to the oscillator. However, such charge pump circuits may be noisy, resulting in an undesirable amount of in-band noise.
Therefore, new phase locked loop designs with new charge pump circuits are desirable.